circuit TLI2C :
  module TLI2C :
    input in_clock : Clock
    input reset : UInt<1>
    output auto_int_out_0 : UInt<1>
    output auto_in_a_ready : UInt<1>
    input auto_in_a_valid : UInt<1>
    input auto_in_a_bits_opcode : UInt<3>
    input auto_in_a_bits_param : UInt<3>
    input auto_in_a_bits_size : UInt<2>
    input auto_in_a_bits_source : UInt<7>
    input auto_in_a_bits_address : UInt<29>
    input auto_in_a_bits_mask : UInt<4>
    input auto_in_a_bits_data : UInt<32>
    input auto_in_b_ready : UInt<1>
    output auto_in_b_valid : UInt<1>
    output auto_in_b_bits_opcode : UInt<3>
    output auto_in_b_bits_param : UInt<2>
    output auto_in_b_bits_size : UInt<2>
    output auto_in_b_bits_source : UInt<7>
    output auto_in_b_bits_address : UInt<29>
    output auto_in_b_bits_mask : UInt<4>
    output auto_in_b_bits_data : UInt<32>
    output auto_in_c_ready : UInt<1>
    input auto_in_c_valid : UInt<1>
    input auto_in_c_bits_opcode : UInt<3>
    input auto_in_c_bits_param : UInt<3>
    input auto_in_c_bits_size : UInt<2>
    input auto_in_c_bits_source : UInt<7>
    input auto_in_c_bits_address : UInt<29>
    input auto_in_c_bits_data : UInt<32>
    input auto_in_c_bits_error : UInt<1>
    input auto_in_d_ready : UInt<1>
    output auto_in_d_valid : UInt<1>
    output auto_in_d_bits_opcode : UInt<3>
    output auto_in_d_bits_param : UInt<2>
    output auto_in_d_bits_size : UInt<2>
    output auto_in_d_bits_source : UInt<7>
    output auto_in_d_bits_sink : UInt<1>
    output auto_in_d_bits_data : UInt<32>
    output auto_in_d_bits_error : UInt<1>
    output auto_in_e_ready : UInt<1>
    input auto_in_e_valid : UInt<1>
    input auto_in_e_bits_sink : UInt<1>
    input io_port_scl_in : UInt<1>
    output io_port_scl_out : UInt<1>
    output io_port_scl_oe : UInt<1>
    input io_port_sda_in : UInt<1>
    output io_port_sda_out : UInt<1>
    output io_port_sda_oe : UInt<1>

 
    wire TLMonitor_reset : UInt<1>
    wire TLMonitor_io_in_a_ready : UInt<1>
    wire TLMonitor_io_in_a_valid : UInt<1>
    wire TLMonitor_io_in_a_bits_opcode : UInt<3>
    wire TLMonitor_io_in_a_bits_param : UInt<3>
    wire TLMonitor_io_in_a_bits_size : UInt<2>
    wire TLMonitor_io_in_a_bits_source : UInt<7>
    wire TLMonitor_io_in_a_bits_address : UInt<29>
    wire TLMonitor_io_in_a_bits_mask : UInt<4>
    wire TLMonitor_io_in_c_valid : UInt<1>
    wire TLMonitor_io_in_d_ready : UInt<1>
    wire TLMonitor_io_in_d_valid : UInt<1>
    wire TLMonitor_io_in_d_bits_opcode : UInt<3>
    wire TLMonitor_io_in_d_bits_size : UInt<2>
    wire TLMonitor_io_in_d_bits_source : UInt<7>
    wire TLMonitor_io_in_e_valid : UInt<1>
    node TLMonitor__T_42 = dshl(UInt<2>("h3"), TLMonitor_io_in_a_bits_size) @[package.scala 104:77]
    node TLMonitor__T_43 = bits(TLMonitor__T_42, 1, 0) @[package.scala 104:82]
    node TLMonitor__T_44 = not(TLMonitor__T_43) @[package.scala 104:46]
    node TLMonitor__GEN_18 = pad(TLMonitor__T_44, 29) @[Edges.scala 21:16]
    node TLMonitor__T_45 = and(TLMonitor_io_in_a_bits_address, TLMonitor__GEN_18) @[Edges.scala 21:16]
    node TLMonitor__T_47 = eq(TLMonitor__T_45, UInt<29>("h0")) @[Edges.scala 21:24]
    node TLMonitor__T_48 = bits(TLMonitor_io_in_a_bits_size, 0, 0) @[OneHot.scala 49:27]
    node TLMonitor__T_50 = dshl(UInt<1>("h1"), TLMonitor__T_48) @[OneHot.scala 50:12]
    node TLMonitor__T_53 = or(TLMonitor__T_50, UInt<2>("h1")) @[Misc.scala 237:54]
    node TLMonitor__T_55 = geq(TLMonitor_io_in_a_bits_size, UInt<2>("h2")) @[Misc.scala 241:21]
    node TLMonitor__T_57 = bits(TLMonitor__T_53, 1, 1) @[Misc.scala 244:26]
    node TLMonitor__T_58 = bits(TLMonitor_io_in_a_bits_address, 1, 1) @[Misc.scala 245:26]
    node TLMonitor__T_60 = not(TLMonitor__T_58) @[Misc.scala 246:20]
    node TLMonitor__T_62 = and(TLMonitor__T_57, TLMonitor__T_60) @[Misc.scala 250:38]
    node TLMonitor__T_63 = or(TLMonitor__T_55, TLMonitor__T_62) @[Misc.scala 250:29]
    node TLMonitor__T_65 = and(TLMonitor__T_57, TLMonitor__T_58) @[Misc.scala 250:38]
    node TLMonitor__T_66 = or(TLMonitor__T_55, TLMonitor__T_65) @[Misc.scala 250:29]
    node TLMonitor__T_67 = bits(TLMonitor__T_53, 0, 0) @[Misc.scala 244:26]
    node TLMonitor__T_68 = bits(TLMonitor_io_in_a_bits_address, 0, 0) @[Misc.scala 245:26]
    node TLMonitor__T_70 = not(TLMonitor__T_68) @[Misc.scala 246:20]
    node TLMonitor__T_71 = and(TLMonitor__T_60, TLMonitor__T_70) @[Misc.scala 249:27]
    node TLMonitor__T_72 = and(TLMonitor__T_67, TLMonitor__T_71) @[Misc.scala 250:38]
    node TLMonitor__T_73 = or(TLMonitor__T_63, TLMonitor__T_72) @[Misc.scala 250:29]
    node TLMonitor__T_74 = and(TLMonitor__T_60, TLMonitor__T_68) @[Misc.scala 249:27]
    node TLMonitor__T_75 = and(TLMonitor__T_67, TLMonitor__T_74) @[Misc.scala 250:38]
    node TLMonitor__T_76 = or(TLMonitor__T_63, TLMonitor__T_75) @[Misc.scala 250:29]
    node TLMonitor__T_77 = and(TLMonitor__T_58, TLMonitor__T_70) @[Misc.scala 249:27]
    node TLMonitor__T_78 = and(TLMonitor__T_67, TLMonitor__T_77) @[Misc.scala 250:38]
    node TLMonitor__T_79 = or(TLMonitor__T_66, TLMonitor__T_78) @[Misc.scala 250:29]
    node TLMonitor__T_80 = and(TLMonitor__T_58, TLMonitor__T_68) @[Misc.scala 249:27]
    node TLMonitor__T_81 = and(TLMonitor__T_67, TLMonitor__T_80) @[Misc.scala 250:38]
    node TLMonitor__T_82 = or(TLMonitor__T_66, TLMonitor__T_81) @[Misc.scala 250:29]
    node TLMonitor__T_83 = cat(TLMonitor__T_76, TLMonitor__T_73) @[Cat.scala 30:58]
    node TLMonitor__T_84 = cat(TLMonitor__T_82, TLMonitor__T_79) @[Cat.scala 30:58]
    node TLMonitor__T_85 = cat(TLMonitor__T_84, TLMonitor__T_83) @[Cat.scala 30:58]
    node TLMonitor__T_87 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h6")) @[Monitor.scala 40:25]
    node TLMonitor__T_92 = xor(TLMonitor_io_in_a_bits_address, UInt<29>("h10016000")) @[Parameters.scala 119:31]
    node TLMonitor__T_93 = cvt(TLMonitor__T_92) @[Parameters.scala 119:49]
    node TLMonitor__T_95 = and(TLMonitor__T_93, SInt<30>("h-1000")) @[Parameters.scala 119:52]
    node TLMonitor__T_96 = asSInt(TLMonitor__T_95) @[Parameters.scala 119:52]
    node TLMonitor__T_98 = eq(TLMonitor__T_96, SInt<30>("h0")) @[Parameters.scala 119:67]
    node TLMonitor__T_105 = not(TLMonitor_reset) @[Monitor.scala 41:14]
    node TLMonitor__T_118 = or(TLMonitor__T_55, TLMonitor_reset) @[Monitor.scala 44:14]
    node TLMonitor__T_120 = not(TLMonitor__T_118) @[Monitor.scala 44:14]
    node TLMonitor__T_122 = or(TLMonitor__T_47, TLMonitor_reset) @[Monitor.scala 45:14]
    node TLMonitor__T_124 = not(TLMonitor__T_122) @[Monitor.scala 45:14]
    node TLMonitor__T_126 = leq(TLMonitor_io_in_a_bits_param, UInt<3>("h2")) @[Bundles.scala 71:27]
    node TLMonitor__T_128 = or(TLMonitor__T_126, TLMonitor_reset) @[Monitor.scala 46:14]
    node TLMonitor__T_130 = not(TLMonitor__T_128) @[Monitor.scala 46:14]
    node TLMonitor__T_131 = not(TLMonitor_io_in_a_bits_mask) @[Monitor.scala 47:15]
    node TLMonitor__T_133 = eq(TLMonitor__T_131, UInt<4>("h0")) @[Monitor.scala 47:28]
    node TLMonitor__T_135 = or(TLMonitor__T_133, TLMonitor_reset) @[Monitor.scala 47:14]
    node TLMonitor__T_137 = not(TLMonitor__T_135) @[Monitor.scala 47:14]
    node TLMonitor__T_139 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h7")) @[Monitor.scala 50:25]
    node TLMonitor__T_184 = neq(TLMonitor_io_in_a_bits_param, UInt<3>("h0")) @[Monitor.scala 57:28]
    node TLMonitor__T_186 = or(TLMonitor__T_184, TLMonitor_reset) @[Monitor.scala 57:14]
    node TLMonitor__T_188 = not(TLMonitor__T_186) @[Monitor.scala 57:14]
    node TLMonitor__T_197 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h4")) @[Monitor.scala 61:25]
    node TLMonitor__T_202 = leq(TLMonitor_io_in_a_bits_size, UInt<2>("h2")) @[Parameters.scala 88:42]
    node TLMonitor__T_213 = and(TLMonitor__T_202, TLMonitor__T_98) @[Parameters.scala 157:56]
    node TLMonitor__T_217 = or(TLMonitor__T_213, TLMonitor_reset) @[Monitor.scala 62:14]
    node TLMonitor__T_219 = not(TLMonitor__T_217) @[Monitor.scala 62:14]
    node TLMonitor__T_229 = eq(TLMonitor_io_in_a_bits_param, UInt<3>("h0")) @[Monitor.scala 65:28]
    node TLMonitor__T_231 = or(TLMonitor__T_229, TLMonitor_reset) @[Monitor.scala 65:14]
    node TLMonitor__T_233 = not(TLMonitor__T_231) @[Monitor.scala 65:14]
    node TLMonitor__T_234 = eq(TLMonitor_io_in_a_bits_mask, TLMonitor__T_85) @[Monitor.scala 66:27]
    node TLMonitor__T_236 = or(TLMonitor__T_234, TLMonitor_reset) @[Monitor.scala 66:14]
    node TLMonitor__T_238 = not(TLMonitor__T_236) @[Monitor.scala 66:14]
    node TLMonitor__T_240 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h0")) @[Monitor.scala 69:25]
    node TLMonitor__T_283 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h1")) @[Monitor.scala 77:25]
    node TLMonitor__T_320 = not(TLMonitor__T_85) @[Monitor.scala 82:30]
    node TLMonitor__T_321 = and(TLMonitor_io_in_a_bits_mask, TLMonitor__T_320) @[Monitor.scala 82:28]
    node TLMonitor__T_323 = eq(TLMonitor__T_321, UInt<4>("h0")) @[Monitor.scala 82:37]
    node TLMonitor__T_325 = or(TLMonitor__T_323, TLMonitor_reset) @[Monitor.scala 82:14]
    node TLMonitor__T_327 = not(TLMonitor__T_325) @[Monitor.scala 82:14]
    node TLMonitor__T_329 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h2")) @[Monitor.scala 85:25]
    node TLMonitor__T_357 = leq(TLMonitor_io_in_a_bits_param, UInt<3>("h4")) @[Bundles.scala 96:33]
    node TLMonitor__T_359 = or(TLMonitor__T_357, TLMonitor_reset) @[Monitor.scala 89:14]
    node TLMonitor__T_361 = not(TLMonitor__T_359) @[Monitor.scala 89:14]
    node TLMonitor__T_368 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h3")) @[Monitor.scala 93:25]
    node TLMonitor__T_396 = leq(TLMonitor_io_in_a_bits_param, UInt<3>("h3")) @[Bundles.scala 103:30]
    node TLMonitor__T_398 = or(TLMonitor__T_396, TLMonitor_reset) @[Monitor.scala 97:14]
    node TLMonitor__T_400 = not(TLMonitor__T_398) @[Monitor.scala 97:14]
    node TLMonitor__T_407 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h5")) @[Monitor.scala 101:25]
    node TLMonitor__T_440 = leq(TLMonitor_io_in_d_bits_opcode, UInt<3>("h6")) @[Bundles.scala 43:24]
    node TLMonitor__T_442 = or(TLMonitor__T_440, TLMonitor_reset) @[Monitor.scala 247:12]
    node TLMonitor__T_444 = not(TLMonitor__T_442) @[Monitor.scala 247:12]
    node TLMonitor__T_468 = eq(TLMonitor_io_in_d_bits_opcode, UInt<3>("h6")) @[Monitor.scala 252:25]
    node TLMonitor__T_478 = geq(TLMonitor_io_in_d_bits_size, UInt<2>("h2")) @[Monitor.scala 255:27]
    node TLMonitor__T_480 = or(TLMonitor__T_478, TLMonitor_reset) @[Monitor.scala 255:14]
    node TLMonitor__T_482 = not(TLMonitor__T_480) @[Monitor.scala 255:14]
    node TLMonitor__T_490 = eq(TLMonitor_io_in_d_bits_opcode, UInt<3>("h4")) @[Monitor.scala 259:25]
    node TLMonitor__T_512 = eq(TLMonitor_io_in_d_bits_opcode, UInt<3>("h5")) @[Monitor.scala 266:25]
    node TLMonitor__T_588 = not(TLMonitor_io_in_c_valid) @[Monitor.scala 309:15]
    node TLMonitor__T_590 = or(TLMonitor__T_588, TLMonitor_reset) @[Monitor.scala 309:14]
    node TLMonitor__T_592 = not(TLMonitor__T_590) @[Monitor.scala 309:14]
    node TLMonitor__T_594 = not(TLMonitor_io_in_e_valid) @[Monitor.scala 310:15]
    node TLMonitor__T_596 = or(TLMonitor__T_594, TLMonitor_reset) @[Monitor.scala 310:14]
    node TLMonitor__T_598 = not(TLMonitor__T_596) @[Monitor.scala 310:14]
    node TLMonitor__T_599 = and(TLMonitor_io_in_a_ready, TLMonitor_io_in_a_valid) @[Bundles.scala 207:36]
    reg TLMonitor__T_613 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_613) @[Edges.scala 220:27]
    node TLMonitor__T_615 = sub(TLMonitor__T_613, UInt<1>("h1")) @[Edges.scala 221:28]
    node TLMonitor__T_617 = tail(TLMonitor__T_615, 1) @[Edges.scala 221:28]
    node TLMonitor__T_619 = not(TLMonitor__T_613) @[Edges.scala 222:25]
    node TLMonitor__T_628 = mux(TLMonitor__T_619, UInt<1>("h0"), TLMonitor__T_617) @[Edges.scala 227:21]
    node TLMonitor__GEN_0 = mux(TLMonitor__T_599, TLMonitor__T_628, TLMonitor__T_613) @[Edges.scala 226:17 227:15 220:27]
    reg TLMonitor__T_630 : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_630) @[Monitor.scala 316:22]
    reg TLMonitor__T_632 : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_632) @[Monitor.scala 317:22]
    reg TLMonitor__T_634 : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_634) @[Monitor.scala 318:22]
    reg TLMonitor__T_636 : UInt<7>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_636) @[Monitor.scala 319:22]
    reg TLMonitor__T_638 : UInt<29>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_638) @[Monitor.scala 320:22]
    node TLMonitor__T_640 = not(TLMonitor__T_619) @[Monitor.scala 321:22]
    node TLMonitor__T_641 = and(TLMonitor_io_in_a_valid, TLMonitor__T_640) @[Monitor.scala 321:19]
    node TLMonitor__T_642 = eq(TLMonitor_io_in_a_bits_opcode, TLMonitor__T_630) @[Monitor.scala 322:29]
    node TLMonitor__T_644 = or(TLMonitor__T_642, TLMonitor_reset) @[Monitor.scala 322:14]
    node TLMonitor__T_646 = not(TLMonitor__T_644) @[Monitor.scala 322:14]
    node TLMonitor__T_647 = eq(TLMonitor_io_in_a_bits_param, TLMonitor__T_632) @[Monitor.scala 323:29]
    node TLMonitor__T_649 = or(TLMonitor__T_647, TLMonitor_reset) @[Monitor.scala 323:14]
    node TLMonitor__T_651 = not(TLMonitor__T_649) @[Monitor.scala 323:14]
    node TLMonitor__T_652 = eq(TLMonitor_io_in_a_bits_size, TLMonitor__T_634) @[Monitor.scala 324:29]
    node TLMonitor__T_654 = or(TLMonitor__T_652, TLMonitor_reset) @[Monitor.scala 324:14]
    node TLMonitor__T_656 = not(TLMonitor__T_654) @[Monitor.scala 324:14]
    node TLMonitor__T_657 = eq(TLMonitor_io_in_a_bits_source, TLMonitor__T_636) @[Monitor.scala 325:29]
    node TLMonitor__T_659 = or(TLMonitor__T_657, TLMonitor_reset) @[Monitor.scala 325:14]
    node TLMonitor__T_661 = not(TLMonitor__T_659) @[Monitor.scala 325:14]
    node TLMonitor__T_662 = eq(TLMonitor_io_in_a_bits_address, TLMonitor__T_638) @[Monitor.scala 326:29]
    node TLMonitor__T_664 = or(TLMonitor__T_662, TLMonitor_reset) @[Monitor.scala 326:14]
    node TLMonitor__T_666 = not(TLMonitor__T_664) @[Monitor.scala 326:14]
    node TLMonitor__T_668 = and(TLMonitor__T_599, TLMonitor__T_619) @[Monitor.scala 328:20]
    node TLMonitor__T_669 = and(TLMonitor_io_in_d_ready, TLMonitor_io_in_d_valid) @[Bundles.scala 207:36]
    reg TLMonitor__T_681 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_681) @[Edges.scala 220:27]
    node TLMonitor__T_683 = sub(TLMonitor__T_681, UInt<1>("h1")) @[Edges.scala 221:28]
    node TLMonitor__T_685 = tail(TLMonitor__T_683, 1) @[Edges.scala 221:28]
    node TLMonitor__T_687 = not(TLMonitor__T_681) @[Edges.scala 222:25]
    node TLMonitor__T_696 = mux(TLMonitor__T_687, UInt<1>("h0"), TLMonitor__T_685) @[Edges.scala 227:21]
    node TLMonitor__GEN_6 = mux(TLMonitor__T_669, TLMonitor__T_696, TLMonitor__T_681) @[Edges.scala 226:17 227:15 220:27]
    reg TLMonitor__T_698 : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_698) @[Monitor.scala 387:22]
    reg TLMonitor__T_702 : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_702) @[Monitor.scala 389:22]
    reg TLMonitor__T_704 : UInt<7>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_704) @[Monitor.scala 390:22]
    node TLMonitor__T_711 = not(TLMonitor__T_687) @[Monitor.scala 393:22]
    node TLMonitor__T_712 = and(TLMonitor_io_in_d_valid, TLMonitor__T_711) @[Monitor.scala 393:19]
    node TLMonitor__T_713 = eq(TLMonitor_io_in_d_bits_opcode, TLMonitor__T_698) @[Monitor.scala 394:29]
    node TLMonitor__T_715 = or(TLMonitor__T_713, TLMonitor_reset) @[Monitor.scala 394:14]
    node TLMonitor__T_717 = not(TLMonitor__T_715) @[Monitor.scala 394:14]
    node TLMonitor__T_723 = eq(TLMonitor_io_in_d_bits_size, TLMonitor__T_702) @[Monitor.scala 396:29]
    node TLMonitor__T_725 = or(TLMonitor__T_723, TLMonitor_reset) @[Monitor.scala 396:14]
    node TLMonitor__T_727 = not(TLMonitor__T_725) @[Monitor.scala 396:14]
    node TLMonitor__T_728 = eq(TLMonitor_io_in_d_bits_source, TLMonitor__T_704) @[Monitor.scala 397:29]
    node TLMonitor__T_730 = or(TLMonitor__T_728, TLMonitor_reset) @[Monitor.scala 397:14]
    node TLMonitor__T_732 = not(TLMonitor__T_730) @[Monitor.scala 397:14]
    node TLMonitor__T_746 = and(TLMonitor__T_669, TLMonitor__T_687) @[Monitor.scala 401:20]
    reg TLMonitor__T_749 : UInt<128>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_749) @[Monitor.scala 420:27]
    reg TLMonitor__T_764 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_764) @[Edges.scala 220:27]
    node TLMonitor__T_766 = sub(TLMonitor__T_764, UInt<1>("h1")) @[Edges.scala 221:28]
    node TLMonitor__T_768 = tail(TLMonitor__T_766, 1) @[Edges.scala 221:28]
    node TLMonitor__T_770 = not(TLMonitor__T_764) @[Edges.scala 222:25]
    node TLMonitor__T_779 = mux(TLMonitor__T_770, UInt<1>("h0"), TLMonitor__T_768) @[Edges.scala 227:21]
    node TLMonitor__GEN_13 = mux(TLMonitor__T_599, TLMonitor__T_779, TLMonitor__T_764) @[Edges.scala 226:17 227:15 220:27]
    reg TLMonitor__T_792 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_792) @[Edges.scala 220:27]
    node TLMonitor__T_794 = sub(TLMonitor__T_792, UInt<1>("h1")) @[Edges.scala 221:28]
    node TLMonitor__T_796 = tail(TLMonitor__T_794, 1) @[Edges.scala 221:28]
    node TLMonitor__T_798 = not(TLMonitor__T_792) @[Edges.scala 222:25]
    node TLMonitor__T_807 = mux(TLMonitor__T_798, UInt<1>("h0"), TLMonitor__T_796) @[Edges.scala 227:21]
    node TLMonitor__GEN_14 = mux(TLMonitor__T_669, TLMonitor__T_807, TLMonitor__T_792) @[Edges.scala 226:17 227:15 220:27]
    node TLMonitor__T_812 = and(TLMonitor__T_599, TLMonitor__T_770) @[Monitor.scala 426:27]
    node TLMonitor__T_816 = dshl(UInt<1>("h1"), TLMonitor_io_in_a_bits_source) @[OneHot.scala 45:35]
    node TLMonitor__T_817 = dshr(TLMonitor__T_749, TLMonitor_io_in_a_bits_source) @[Monitor.scala 428:23]
    node TLMonitor__T_818 = bits(TLMonitor__T_817, 0, 0) @[Monitor.scala 428:23]
    node TLMonitor__T_820 = not(TLMonitor__T_818) @[Monitor.scala 428:14]
    node TLMonitor__T_822 = or(TLMonitor__T_820, TLMonitor_reset) @[Monitor.scala 428:13]
    node TLMonitor__T_824 = not(TLMonitor__T_822) @[Monitor.scala 428:13]
    node TLMonitor__GEN_15 = mux(TLMonitor__T_812, TLMonitor__T_816, UInt<128>("h0")) @[Monitor.scala 426:72 427:13]
    node TLMonitor__T_831 = and(TLMonitor__T_669, TLMonitor__T_798) @[Monitor.scala 433:27]
    node TLMonitor__T_835 = not(TLMonitor__T_468) @[Monitor.scala 433:75]
    node TLMonitor__T_836 = and(TLMonitor__T_831, TLMonitor__T_835) @[Monitor.scala 433:72]
    node TLMonitor__T_838 = dshl(UInt<1>("h1"), TLMonitor_io_in_d_bits_source) @[OneHot.scala 45:35]
    node TLMonitor__T_839 = or(TLMonitor__GEN_15, TLMonitor__T_749) @[Monitor.scala 435:21]
    node TLMonitor__T_840 = dshr(TLMonitor__T_839, TLMonitor_io_in_d_bits_source) @[Monitor.scala 435:32]
    node TLMonitor__T_841 = bits(TLMonitor__T_840, 0, 0) @[Monitor.scala 435:32]
    node TLMonitor__T_843 = or(TLMonitor__T_841, TLMonitor_reset) @[Monitor.scala 435:13]
    node TLMonitor__T_845 = not(TLMonitor__T_843) @[Monitor.scala 435:13]
    node TLMonitor__GEN_16 = mux(TLMonitor__T_836, TLMonitor__T_838, UInt<128>("h0")) @[Monitor.scala 433:91 434:13]
    node TLMonitor__T_846 = or(TLMonitor__T_749, TLMonitor__GEN_15) @[Monitor.scala 442:27]
    node TLMonitor__T_847 = not(TLMonitor__GEN_16) @[Monitor.scala 442:38]
    node TLMonitor__T_848 = and(TLMonitor__T_846, TLMonitor__T_847) @[Monitor.scala 442:36]
    node TLMonitor__GEN_19 = and(TLMonitor_io_in_a_valid, TLMonitor__T_87) @[Monitor.scala 41:14]
    node TLMonitor__GEN_31 = and(TLMonitor_io_in_a_valid, TLMonitor__T_139) @[Monitor.scala 51:14]
    node TLMonitor__GEN_45 = and(TLMonitor_io_in_a_valid, TLMonitor__T_197) @[Monitor.scala 62:14]
    node TLMonitor__GEN_53 = and(TLMonitor_io_in_a_valid, TLMonitor__T_240) @[Monitor.scala 70:14]
    node TLMonitor__GEN_61 = and(TLMonitor_io_in_a_valid, TLMonitor__T_283) @[Monitor.scala 78:14]
    node TLMonitor__GEN_69 = and(TLMonitor_io_in_a_valid, TLMonitor__T_329) @[Monitor.scala 86:14]
    node TLMonitor__GEN_77 = and(TLMonitor_io_in_a_valid, TLMonitor__T_368) @[Monitor.scala 94:14]
    node TLMonitor__GEN_85 = and(TLMonitor_io_in_a_valid, TLMonitor__T_407) @[Monitor.scala 102:14]
    node TLMonitor__GEN_91 = and(TLMonitor_io_in_d_valid, TLMonitor__T_468) @[Monitor.scala 255:14]
    node TLMonitor__GEN_93 = and(TLMonitor_io_in_d_valid, TLMonitor__T_490) @[Monitor.scala 262:14]
    node TLMonitor__GEN_95 = and(TLMonitor_io_in_d_valid, TLMonitor__T_512) @[Monitor.scala 269:14]
    TLMonitor__T_613 <= mux(TLMonitor_reset, UInt<1>("h0"), TLMonitor__GEN_0) @[Edges.scala 220:{27,27}]
    TLMonitor__T_630 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_opcode, TLMonitor__T_630) @[Monitor.scala 328:32 329:15 316:22]
    TLMonitor__T_632 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_param, TLMonitor__T_632) @[Monitor.scala 328:32 330:15 317:22]
    TLMonitor__T_634 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_size, TLMonitor__T_634) @[Monitor.scala 328:32 331:15 318:22]
    TLMonitor__T_636 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_source, TLMonitor__T_636) @[Monitor.scala 328:32 332:15 319:22]
    TLMonitor__T_638 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_address, TLMonitor__T_638) @[Monitor.scala 328:32 333:15 320:22]
    TLMonitor__T_681 <= mux(TLMonitor_reset, UInt<1>("h0"), TLMonitor__GEN_6) @[Edges.scala 220:{27,27}]
    TLMonitor__T_698 <= mux(TLMonitor__T_746, TLMonitor_io_in_d_bits_opcode, TLMonitor__T_698) @[Monitor.scala 401:32 402:15 387:22]
    TLMonitor__T_702 <= mux(TLMonitor__T_746, TLMonitor_io_in_d_bits_size, TLMonitor__T_702) @[Monitor.scala 401:32 404:15 389:22]
    TLMonitor__T_704 <= mux(TLMonitor__T_746, TLMonitor_io_in_d_bits_source, TLMonitor__T_704) @[Monitor.scala 401:32 405:15 390:22]
    TLMonitor__T_749 <= mux(TLMonitor_reset, UInt<128>("h0"), TLMonitor__T_848) @[Monitor.scala 420:{27,27} 442:14]
    TLMonitor__T_764 <= mux(TLMonitor_reset, UInt<1>("h0"), TLMonitor__GEN_13) @[Edges.scala 220:{27,27}]
    TLMonitor__T_792 <= mux(TLMonitor_reset, UInt<1>("h0"), TLMonitor__GEN_14) @[Edges.scala 220:{27,27}]

    reg prescaler_hi : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), prescaler_hi) @[I2C.scala 109:25]
    reg prescaler_lo : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), prescaler_lo) @[I2C.scala 109:25]
    reg control_coreEn : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), control_coreEn) @[I2C.scala 110:25]
    reg control_intEn : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), control_intEn) @[I2C.scala 110:25]
    reg transmitData : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), transmitData) @[I2C.scala 111:25]
    reg receivedData : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), receivedData) @[I2C.scala 112:25]
    reg cmd_start : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), cmd_start) @[I2C.scala 113:25]
    reg cmd_stop : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), cmd_stop) @[I2C.scala 113:25]
    reg cmd_read : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), cmd_read) @[I2C.scala 113:25]
    reg cmd_write : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), cmd_write) @[I2C.scala 113:25]
    reg cmd_ack : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), cmd_ack) @[I2C.scala 113:25]
    reg cmd_irqAck : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), cmd_irqAck) @[I2C.scala 113:25]
    reg status_receivedAck : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), status_receivedAck) @[I2C.scala 114:25]
    reg status_busy : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), status_busy) @[I2C.scala 114:25]
    reg status_arbLost : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), status_arbLost) @[I2C.scala 114:25]
    reg status_transferInProgress : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), status_transferInProgress) @[I2C.scala 114:25]
    reg status_irqFlag : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), status_irqFlag) @[I2C.scala 114:25]
    reg filterCnt : UInt<14>, in_clock with :
      reset => (UInt<1>("h0"), filterCnt) @[I2C.scala 123:22]
    node _T_234 = not(control_coreEn) @[I2C.scala 124:10]
    node _T_237 = neq(filterCnt, UInt<14>("h0")) @[I2C.scala 126:28]
    node _T_239 = not(_T_237) @[I2C.scala 126:16]
    node _T_240 = cat(prescaler_hi, prescaler_lo) @[Cat.scala 30:58]
    node _T_241 = shr(_T_240, 2) @[I2C.scala 127:50]
    node _T_243 = sub(filterCnt, UInt<14>("h1")) @[I2C.scala 129:28]
    node _T_245 = tail(_T_243, 1) @[I2C.scala 129:28]
    node _GEN_0 = mux(_T_239, _T_241, _T_245) @[I2C.scala 126:34 127:15 129:15]
    node _GEN_1 = mux(_T_234, UInt<14>("h0"), _GEN_0) @[I2C.scala 124:28 125:15]
    reg fSCL : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), fSCL) @[I2C.scala 132:22]
    reg fSDA : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), fSDA) @[I2C.scala 133:22]
    node _T_254 = cat(fSCL, io_port_scl_in) @[Cat.scala 30:58]
    node _T_255 = cat(fSDA, io_port_sda_in) @[Cat.scala 30:58]
    node _GEN_2 = mux(_T_239, _T_254, pad(fSCL, 4)) @[I2C.scala 134:27 135:10 132:22]
    node _GEN_3 = mux(_T_239, _T_255, pad(fSDA, 4)) @[I2C.scala 134:27 136:10 133:22]
    node _T_257 = bits(fSCL, 0, 0) @[Misc.scala 208:40]
    node _T_258 = bits(fSCL, 1, 1) @[Misc.scala 208:40]
    node _T_259 = bits(fSCL, 2, 2) @[Misc.scala 208:40]
    node _T_260 = and(_T_257, _T_258) @[Misc.scala 202:48]
    node _T_261 = and(_T_257, _T_259) @[Misc.scala 202:48]
    node _T_262 = or(_T_260, _T_261) @[Misc.scala 203:22]
    node _T_263 = and(_T_258, _T_259) @[Misc.scala 202:48]
    node _T_264 = or(_T_262, _T_263) @[Misc.scala 203:22]
    reg sSCL : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), sSCL) @[I2C.scala 139:22]
    node _T_267 = bits(fSDA, 0, 0) @[Misc.scala 208:40]
    node _T_268 = bits(fSDA, 1, 1) @[Misc.scala 208:40]
    node _T_269 = bits(fSDA, 2, 2) @[Misc.scala 208:40]
    node _T_270 = and(_T_267, _T_268) @[Misc.scala 202:48]
    node _T_271 = and(_T_267, _T_269) @[Misc.scala 202:48]
    node _T_272 = or(_T_270, _T_271) @[Misc.scala 203:22]
    node _T_273 = and(_T_268, _T_269) @[Misc.scala 202:48]
    node _T_274 = or(_T_272, _T_273) @[Misc.scala 203:22]
    reg sSDA : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), sSDA) @[I2C.scala 140:22]
    reg dSCL : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), dSCL) @[I2C.scala 142:22]
    reg dSDA : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), dSDA) @[I2C.scala 143:22]
    reg dSCLOen : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), dSCLOen) @[I2C.scala 145:22]
    node _T_283 = not(sSDA) @[I2C.scala 149:46]
    node _T_284 = and(_T_283, dSDA) @[I2C.scala 149:52]
    node _T_285 = and(_T_284, sSCL) @[I2C.scala 149:61]
    reg startCond : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), startCond) @[I2C.scala 149:22]
    node _T_289 = not(dSDA) @[I2C.scala 150:55]
    node _T_290 = and(sSDA, _T_289) @[I2C.scala 150:52]
    node _T_291 = and(_T_290, sSCL) @[I2C.scala 150:61]
    reg stopCond : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), stopCond) @[I2C.scala 150:22]
    node _T_294 = not(sSCL) @[I2C.scala 154:27]
    node _T_295 = and(dSCL, _T_294) @[I2C.scala 154:24]
    node sclSync = and(_T_295, io_port_scl_oe) @[I2C.scala 154:33]
    reg slaveWait : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), slaveWait) @[I2C.scala 158:22]
    node _T_299 = not(dSCLOen) @[I2C.scala 159:35]
    node _T_300 = and(io_port_scl_oe, _T_299) @[I2C.scala 159:32]
    node _T_303 = and(_T_300, _T_294) @[I2C.scala 159:44]
    node _T_306 = and(slaveWait, _T_294) @[I2C.scala 159:68]
    node _T_307 = or(_T_303, _T_306) @[I2C.scala 159:54]
    reg clkEn : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), clkEn) @[I2C.scala 161:22]
    reg cnt : UInt<16>, in_clock with :
      reset => (UInt<1>("h0"), cnt) @[I2C.scala 162:22]
    node _T_313 = neq(cnt, UInt<16>("h0")) @[I2C.scala 165:15]
    node _T_315 = not(_T_313) @[I2C.scala 165:9]
    node _T_318 = or(_T_315, _T_234) @[I2C.scala 165:20]
    node _T_319 = or(_T_318, sclSync) @[I2C.scala 165:39]
    node _T_324 = sub(cnt, UInt<16>("h1")) @[I2C.scala 173:18]
    node _T_326 = tail(_T_324, 1) @[I2C.scala 173:18]
    node _GEN_5 = mux(slaveWait, cnt, _T_326) @[I2C.scala 162:22 169:25 173:11]
    node _GEN_6 = mux(_T_319, _T_240, _GEN_5) @[I2C.scala 165:52 166:11]
    reg sclOen : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), sclOen) @[I2C.scala 177:23]
    reg sdaOen : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), sdaOen) @[I2C.scala 180:23]
    reg sdaChk : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), sdaChk) @[I2C.scala 183:23]
    reg transmitBit : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), transmitBit) @[I2C.scala 185:24]
    reg receivedBit : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), receivedBit) @[I2C.scala 186:24]
    node _T_342 = not(dSCL) @[I2C.scala 187:17]
    node _T_343 = and(sSCL, _T_342) @[I2C.scala 187:14]
    reg bitCmd : UInt<4>, in_clock with :
      reset => (UInt<1>("h0"), bitCmd) @[I2C.scala 191:24]
    reg bitCmdStop : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), bitCmdStop) @[I2C.scala 192:24]
    node _T_348 = eq(bitCmd, UInt<4>("h2")) @[I2C.scala 194:26]
    node _GEN_9 = mux(clkEn, _T_348, bitCmdStop) @[I2C.scala 193:16 194:16 192:24]
    reg bitCmdAck : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), bitCmdAck) @[I2C.scala 196:24]
    reg bitState : UInt<5>, in_clock with :
      reset => (UInt<1>("h0"), bitState) @[I2C.scala 203:24]
    node _T_356 = and(sdaChk, _T_283) @[I2C.scala 205:56]
    node _T_357 = and(_T_356, sdaOen) @[I2C.scala 205:65]
    node _T_358 = neq(bitState, UInt<5>("h0")) @[I2C.scala 205:89]
    node _T_359 = and(_T_358, stopCond) @[I2C.scala 205:105]
    node _T_361 = not(bitCmdStop) @[I2C.scala 205:120]
    node _T_362 = and(_T_359, _T_361) @[I2C.scala 205:117]
    node _T_363 = or(_T_357, _T_362) @[I2C.scala 205:76]
    reg arbLost : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), arbLost) @[I2C.scala 205:24]
    node _T_370 = eq(UInt<5>("h0"), bitState) @[Conditional.scala 37:30]
    node _T_371 = eq(UInt<4>("h1"), bitCmd) @[Conditional.scala 37:30]
    node _T_372 = eq(UInt<4>("h2"), bitCmd) @[Conditional.scala 37:30]
    node _T_373 = eq(UInt<4>("h4"), bitCmd) @[Conditional.scala 37:30]
    node _T_374 = eq(UInt<4>("h8"), bitCmd) @[Conditional.scala 37:30]
    node _GEN_10 = mux(_T_374, UInt<5>("ha"), bitState) @[Conditional.scala 39:67 I2C.scala 203:24 225:43]
    node _GEN_11 = mux(_T_373, UInt<5>("he"), _GEN_10) @[Conditional.scala 39:67 I2C.scala 224:43]
    node _GEN_12 = mux(_T_372, UInt<5>("h6"), _GEN_11) @[Conditional.scala 39:67 I2C.scala 223:43]
    node _GEN_13 = mux(_T_371, UInt<5>("h1"), _GEN_12) @[Conditional.scala 40:58 I2C.scala 222:43]
    node _T_376 = eq(UInt<5>("h1"), bitState) @[Conditional.scala 37:30]
    node _T_379 = eq(UInt<5>("h2"), bitState) @[Conditional.scala 37:30]
    node _T_383 = eq(UInt<5>("h3"), bitState) @[Conditional.scala 37:30]
    node _T_387 = eq(UInt<5>("h4"), bitState) @[Conditional.scala 37:30]
    node _T_391 = eq(UInt<5>("h5"), bitState) @[Conditional.scala 37:30]
    node _T_396 = eq(UInt<5>("h6"), bitState) @[Conditional.scala 37:30]
    node _T_400 = eq(UInt<5>("h7"), bitState) @[Conditional.scala 37:30]
    node _T_404 = eq(UInt<5>("h8"), bitState) @[Conditional.scala 37:30]
    node _T_408 = eq(UInt<5>("h9"), bitState) @[Conditional.scala 37:30]
    node _T_413 = eq(UInt<5>("ha"), bitState) @[Conditional.scala 37:30]
    node _T_417 = eq(UInt<5>("hb"), bitState) @[Conditional.scala 37:30]
    node _T_421 = eq(UInt<5>("hc"), bitState) @[Conditional.scala 37:30]
    node _T_425 = eq(UInt<5>("hd"), bitState) @[Conditional.scala 37:30]
    node _T_430 = eq(UInt<5>("he"), bitState) @[Conditional.scala 37:30]
    node _T_433 = eq(UInt<5>("hf"), bitState) @[Conditional.scala 37:30]
    node _T_436 = eq(UInt<5>("h10"), bitState) @[Conditional.scala 37:30]
    node _T_439 = eq(UInt<5>("h11"), bitState) @[Conditional.scala 37:30]
    node _GEN_14 = mux(_T_439, UInt<5>("h0"), bitState) @[Conditional.scala 39:67 I2C.scala 333:21 203:24]
    node _GEN_16 = mux(_T_439, UInt<1>("h0"), sclOen) @[Conditional.scala 39:67 I2C.scala 335:21 177:23]
    node _GEN_17 = mux(_T_439, transmitBit, sdaOen) @[Conditional.scala 39:67 I2C.scala 336:21 180:23]
    node _GEN_18 = mux(_T_439, UInt<1>("h0"), sdaChk) @[Conditional.scala 39:67 I2C.scala 337:21 183:23]
    node _GEN_19 = mux(_T_436, UInt<5>("h11"), _GEN_14) @[Conditional.scala 39:67 I2C.scala 327:21]
    node _GEN_20 = or(_T_436, _GEN_16) @[Conditional.scala 39:67 I2C.scala 328:21]
    node _GEN_21 = mux(_T_436, transmitBit, _GEN_17) @[Conditional.scala 39:67 I2C.scala 329:21]
    node _GEN_22 = or(_T_436, _GEN_18) @[Conditional.scala 39:67 I2C.scala 330:21]
    node _GEN_23 = mux(_T_436, UInt<1>("h0"), _T_439) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_24 = mux(_T_433, UInt<5>("h10"), _GEN_19) @[Conditional.scala 39:67 I2C.scala 321:21]
    node _GEN_25 = or(_T_433, _GEN_20) @[Conditional.scala 39:67 I2C.scala 322:21]
    node _GEN_26 = mux(_T_433, transmitBit, _GEN_21) @[Conditional.scala 39:67 I2C.scala 323:21]
    node _GEN_27 = mux(_T_433, UInt<1>("h0"), _GEN_22) @[Conditional.scala 39:67 I2C.scala 324:21]
    node _GEN_28 = mux(_T_433, UInt<1>("h0"), _GEN_23) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_29 = mux(_T_430, UInt<5>("hf"), _GEN_24) @[Conditional.scala 39:67 I2C.scala 315:21]
    node _GEN_30 = mux(_T_430, UInt<1>("h0"), _GEN_25) @[Conditional.scala 39:67 I2C.scala 316:21]
    node _GEN_31 = mux(_T_430, transmitBit, _GEN_26) @[Conditional.scala 39:67 I2C.scala 317:21]
    node _GEN_32 = mux(_T_430, UInt<1>("h0"), _GEN_27) @[Conditional.scala 39:67 I2C.scala 318:21]
    node _GEN_33 = mux(_T_430, UInt<1>("h0"), _GEN_28) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_34 = mux(_T_425, UInt<5>("h0"), _GEN_29) @[Conditional.scala 39:67 I2C.scala 307:21]
    node _GEN_35 = or(_T_425, _GEN_33) @[Conditional.scala 39:67 I2C.scala 308:21]
    node _GEN_36 = mux(_T_425, UInt<1>("h0"), _GEN_30) @[Conditional.scala 39:67 I2C.scala 309:21]
    node _GEN_37 = or(_T_425, _GEN_31) @[Conditional.scala 39:67 I2C.scala 310:21]
    node _GEN_38 = mux(_T_425, UInt<1>("h0"), _GEN_32) @[Conditional.scala 39:67 I2C.scala 311:21]
    node _GEN_39 = mux(_T_421, UInt<5>("hd"), _GEN_34) @[Conditional.scala 39:67 I2C.scala 301:21]
    node _GEN_40 = or(_T_421, _GEN_36) @[Conditional.scala 39:67 I2C.scala 302:21]
    node _GEN_41 = or(_T_421, _GEN_37) @[Conditional.scala 39:67 I2C.scala 303:21]
    node _GEN_42 = mux(_T_421, UInt<1>("h0"), _GEN_38) @[Conditional.scala 39:67 I2C.scala 304:21]
    node _GEN_43 = mux(_T_421, UInt<1>("h0"), _GEN_35) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_44 = mux(_T_417, UInt<5>("hc"), _GEN_39) @[Conditional.scala 39:67 I2C.scala 295:21]
    node _GEN_45 = or(_T_417, _GEN_40) @[Conditional.scala 39:67 I2C.scala 296:21]
    node _GEN_46 = or(_T_417, _GEN_41) @[Conditional.scala 39:67 I2C.scala 297:21]
    node _GEN_47 = mux(_T_417, UInt<1>("h0"), _GEN_42) @[Conditional.scala 39:67 I2C.scala 298:21]
    node _GEN_48 = mux(_T_417, UInt<1>("h0"), _GEN_43) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_49 = mux(_T_413, UInt<5>("hb"), _GEN_44) @[Conditional.scala 39:67 I2C.scala 289:21]
    node _GEN_50 = mux(_T_413, UInt<1>("h0"), _GEN_45) @[Conditional.scala 39:67 I2C.scala 290:21]
    node _GEN_51 = or(_T_413, _GEN_46) @[Conditional.scala 39:67 I2C.scala 291:21]
    node _GEN_52 = mux(_T_413, UInt<1>("h0"), _GEN_47) @[Conditional.scala 39:67 I2C.scala 292:21]
    node _GEN_53 = mux(_T_413, UInt<1>("h0"), _GEN_48) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_54 = mux(_T_408, UInt<5>("h0"), _GEN_49) @[Conditional.scala 39:67 I2C.scala 281:21]
    node _GEN_55 = or(_T_408, _GEN_53) @[Conditional.scala 39:67 I2C.scala 282:21]
    node _GEN_56 = or(_T_408, _GEN_50) @[Conditional.scala 39:67 I2C.scala 283:21]
    node _GEN_57 = or(_T_408, _GEN_51) @[Conditional.scala 39:67 I2C.scala 284:21]
    node _GEN_58 = mux(_T_408, UInt<1>("h0"), _GEN_52) @[Conditional.scala 39:67 I2C.scala 285:21]
    node _GEN_59 = mux(_T_404, UInt<5>("h9"), _GEN_54) @[Conditional.scala 39:67 I2C.scala 275:21]
    node _GEN_60 = or(_T_404, _GEN_56) @[Conditional.scala 39:67 I2C.scala 276:21]
    node _GEN_61 = mux(_T_404, UInt<1>("h0"), _GEN_57) @[Conditional.scala 39:67 I2C.scala 277:21]
    node _GEN_62 = mux(_T_404, UInt<1>("h0"), _GEN_58) @[Conditional.scala 39:67 I2C.scala 278:21]
    node _GEN_63 = mux(_T_404, UInt<1>("h0"), _GEN_55) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_64 = mux(_T_400, UInt<5>("h8"), _GEN_59) @[Conditional.scala 39:67 I2C.scala 269:21]
    node _GEN_65 = or(_T_400, _GEN_60) @[Conditional.scala 39:67 I2C.scala 270:21]
    node _GEN_66 = mux(_T_400, UInt<1>("h0"), _GEN_61) @[Conditional.scala 39:67 I2C.scala 271:21]
    node _GEN_67 = mux(_T_400, UInt<1>("h0"), _GEN_62) @[Conditional.scala 39:67 I2C.scala 272:21]
    node _GEN_68 = mux(_T_400, UInt<1>("h0"), _GEN_63) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_69 = mux(_T_396, UInt<5>("h7"), _GEN_64) @[Conditional.scala 39:67 I2C.scala 263:21]
    node _GEN_70 = mux(_T_396, UInt<1>("h0"), _GEN_65) @[Conditional.scala 39:67 I2C.scala 264:21]
    node _GEN_71 = mux(_T_396, UInt<1>("h0"), _GEN_66) @[Conditional.scala 39:67 I2C.scala 265:21]
    node _GEN_72 = mux(_T_396, UInt<1>("h0"), _GEN_67) @[Conditional.scala 39:67 I2C.scala 266:21]
    node _GEN_73 = mux(_T_396, UInt<1>("h0"), _GEN_68) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_74 = mux(_T_391, UInt<5>("h0"), _GEN_69) @[Conditional.scala 39:67 I2C.scala 255:21]
    node _GEN_75 = or(_T_391, _GEN_73) @[Conditional.scala 39:67 I2C.scala 256:21]
    node _GEN_76 = mux(_T_391, UInt<1>("h0"), _GEN_70) @[Conditional.scala 39:67 I2C.scala 257:21]
    node _GEN_77 = mux(_T_391, UInt<1>("h0"), _GEN_71) @[Conditional.scala 39:67 I2C.scala 258:21]
    node _GEN_78 = mux(_T_391, UInt<1>("h0"), _GEN_72) @[Conditional.scala 39:67 I2C.scala 259:21]
    node _GEN_79 = mux(_T_387, UInt<5>("h5"), _GEN_74) @[Conditional.scala 39:67 I2C.scala 249:21]
    node _GEN_80 = or(_T_387, _GEN_76) @[Conditional.scala 39:67 I2C.scala 250:21]
    node _GEN_81 = mux(_T_387, UInt<1>("h0"), _GEN_77) @[Conditional.scala 39:67 I2C.scala 251:21]
    node _GEN_82 = mux(_T_387, UInt<1>("h0"), _GEN_78) @[Conditional.scala 39:67 I2C.scala 252:21]
    node _GEN_83 = mux(_T_387, UInt<1>("h0"), _GEN_75) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_84 = mux(_T_383, UInt<5>("h4"), _GEN_79) @[Conditional.scala 39:67 I2C.scala 243:21]
    node _GEN_85 = or(_T_383, _GEN_80) @[Conditional.scala 39:67 I2C.scala 244:21]
    node _GEN_86 = mux(_T_383, UInt<1>("h0"), _GEN_81) @[Conditional.scala 39:67 I2C.scala 245:21]
    node _GEN_87 = mux(_T_383, UInt<1>("h0"), _GEN_82) @[Conditional.scala 39:67 I2C.scala 246:21]
    node _GEN_88 = mux(_T_383, UInt<1>("h0"), _GEN_83) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_89 = mux(_T_379, UInt<5>("h3"), _GEN_84) @[Conditional.scala 39:67 I2C.scala 237:21]
    node _GEN_90 = or(_T_379, _GEN_85) @[Conditional.scala 39:67 I2C.scala 238:21]
    node _GEN_91 = or(_T_379, _GEN_86) @[Conditional.scala 39:67 I2C.scala 239:21]
    node _GEN_92 = mux(_T_379, UInt<1>("h0"), _GEN_87) @[Conditional.scala 39:67 I2C.scala 240:21]
    node _GEN_93 = mux(_T_379, UInt<1>("h0"), _GEN_88) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_94 = mux(_T_376, UInt<5>("h2"), _GEN_89) @[Conditional.scala 39:67 I2C.scala 231:21]
    node _GEN_95 = mux(_T_376, sclOen, _GEN_90) @[Conditional.scala 39:67 I2C.scala 232:21]
    node _GEN_96 = or(_T_376, _GEN_91) @[Conditional.scala 39:67 I2C.scala 233:21]
    node _GEN_97 = mux(_T_376, UInt<1>("h0"), _GEN_92) @[Conditional.scala 39:67 I2C.scala 234:21]
    node _GEN_98 = mux(_T_376, UInt<1>("h0"), _GEN_93) @[Conditional.scala 39:67 I2C.scala 216:15]
    node _GEN_99 = mux(_T_370, _GEN_13, _GEN_94) @[Conditional.scala 40:58]
    node _GEN_100 = mux(_T_370, UInt<1>("h0"), _GEN_97) @[Conditional.scala 40:58 I2C.scala 227:18]
    node _GEN_101 = mux(_T_370, sclOen, _GEN_95) @[Conditional.scala 40:58 I2C.scala 177:23]
    node _GEN_102 = mux(_T_370, sdaOen, _GEN_96) @[Conditional.scala 40:58 I2C.scala 180:23]
    node _GEN_103 = mux(_T_370, UInt<1>("h0"), _GEN_98) @[Conditional.scala 40:58 I2C.scala 216:15]
    node _GEN_104 = mux(clkEn, _GEN_99, bitState) @[I2C.scala 218:18 203:24]
    node _GEN_105 = mux(clkEn, _GEN_100, sdaChk) @[I2C.scala 218:18 183:23]
    node _GEN_106 = mux(clkEn, _GEN_101, sclOen) @[I2C.scala 218:18 177:23]
    node _GEN_107 = mux(clkEn, _GEN_102, sdaOen) @[I2C.scala 218:18 180:23]
    node _GEN_108 = and(clkEn, _GEN_103) @[I2C.scala 216:15 218:18]
    node _GEN_109 = mux(arbLost, UInt<5>("h0"), _GEN_104) @[I2C.scala 208:18 209:15]
    node _GEN_110 = mux(arbLost, UInt<1>("h0"), _GEN_108) @[I2C.scala 208:18 210:15]
    node _GEN_111 = or(arbLost, _GEN_106) @[I2C.scala 208:18 211:15]
    node _GEN_112 = or(arbLost, _GEN_107) @[I2C.scala 208:18 212:15]
    node _GEN_113 = mux(arbLost, UInt<1>("h0"), _GEN_105) @[I2C.scala 208:18 213:15]
    reg load : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), load) @[I2C.scala 345:24]
    reg shift : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), shift) @[I2C.scala 346:24]
    reg cmdAck : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), cmdAck) @[I2C.scala 347:24]
    reg receivedAck : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), receivedAck) @[I2C.scala 348:24]
    node _T_451 = or(cmd_read, cmd_write) @[I2C.scala 349:31]
    node _T_452 = or(_T_451, cmd_stop) @[I2C.scala 349:43]
    node _T_454 = not(cmdAck) @[I2C.scala 349:57]
    node go = and(_T_452, _T_454) @[I2C.scala 349:55]
    reg bitCnt : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), bitCnt) @[I2C.scala 351:24]
    node _T_459 = sub(bitCnt, UInt<3>("h1")) @[I2C.scala 356:22]
    node _T_461 = tail(_T_459, 1) @[I2C.scala 356:22]
    node _GEN_114 = mux(shift, _T_461, bitCnt) @[I2C.scala 355:21 356:12 351:24]
    node _GEN_115 = mux(load, UInt<3>("h7"), _GEN_114) @[I2C.scala 352:15 353:12]
    node _T_463 = neq(bitCnt, UInt<3>("h0")) @[I2C.scala 358:30]
    node bitCntDone = not(_T_463) @[I2C.scala 358:21]
    node _T_465 = cat(receivedData, receivedBit) @[Cat.scala 30:58]
    node _GEN_116 = mux(shift, _T_465, pad(receivedData, 9)) @[I2C.scala 364:21 365:18 112:25]
    node _GEN_117 = mux(load, pad(transmitData, 9), _GEN_116) @[I2C.scala 361:15 362:18]
    reg byteState : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), byteState) @[I2C.scala 369:24]
    node _T_473 = bits(receivedData, 7, 7) @[I2C.scala 381:32]
    node _T_477 = eq(UInt<3>("h0"), byteState) @[Conditional.scala 37:30]
    node _GEN_118 = mux(cmd_write, UInt<3>("h3"), UInt<3>("h5")) @[I2C.scala 397:33 398:23 402:23]
    node _GEN_119 = mux(cmd_write, UInt<3>("h4"), UInt<3>("h2")) @[I2C.scala 397:33 399:23 403:23]
    node _GEN_120 = mux(cmd_read, UInt<3>("h2"), _GEN_118) @[I2C.scala 393:32 394:23]
    node _GEN_121 = mux(cmd_read, UInt<4>("h8"), pad(_GEN_119, 4)) @[I2C.scala 393:32 395:23]
    node _GEN_122 = mux(cmd_start, UInt<3>("h1"), _GEN_120) @[I2C.scala 389:28 390:23]
    node _GEN_123 = mux(cmd_start, UInt<4>("h1"), _GEN_121) @[I2C.scala 389:28 391:23]
    node _GEN_124 = mux(go, _GEN_122, byteState) @[I2C.scala 388:19 369:24]
    node _GEN_125 = mux(go, _GEN_123, bitCmd) @[I2C.scala 388:19 191:24]
    node _T_479 = eq(UInt<3>("h1"), byteState) @[Conditional.scala 37:30]
    node _GEN_127 = mux(cmd_read, UInt<3>("h2"), UInt<3>("h3")) @[I2C.scala 411:27 412:23 416:23]
    node _GEN_128 = mux(cmd_read, UInt<4>("h8"), UInt<4>("h4")) @[I2C.scala 411:27 413:23 417:23]
    node _GEN_129 = mux(bitCmdAck, _GEN_127, byteState) @[I2C.scala 369:24 410:26]
    node _GEN_130 = mux(bitCmdAck, _GEN_128, bitCmd) @[I2C.scala 191:24 410:26]
    node _T_481 = eq(UInt<3>("h3"), byteState) @[Conditional.scala 37:30]
    node _GEN_132 = mux(bitCntDone, UInt<3>("h4"), UInt<3>("h3")) @[I2C.scala 425:29 426:23 430:23]
    node _GEN_133 = mux(bitCntDone, UInt<4>("h8"), UInt<4>("h4")) @[I2C.scala 425:29 427:23 431:23]
    node _GEN_134 = mux(bitCntDone, UInt<1>("h0"), UInt<1>("h1")) @[I2C.scala 382:17 425:29 432:23]
    node _GEN_135 = mux(bitCmdAck, _GEN_132, byteState) @[I2C.scala 369:24 424:26]
    node _GEN_136 = mux(bitCmdAck, _GEN_133, bitCmd) @[I2C.scala 191:24 424:26]
    node _GEN_137 = and(bitCmdAck, _GEN_134) @[I2C.scala 382:17 424:26]
    node _T_483 = eq(UInt<3>("h2"), byteState) @[Conditional.scala 37:30]
    node _GEN_138 = mux(bitCntDone, UInt<3>("h4"), UInt<3>("h2")) @[I2C.scala 438:29 439:23 443:23]
    node _GEN_139 = mux(bitCntDone, UInt<4>("h4"), UInt<4>("h8")) @[I2C.scala 438:29 440:23 444:23]
    node _GEN_140 = mux(bitCmdAck, _GEN_138, byteState) @[I2C.scala 369:24 437:26]
    node _GEN_141 = mux(bitCmdAck, _GEN_139, bitCmd) @[I2C.scala 191:24 437:26]
    node _GEN_142 = mux(bitCmdAck, cmd_ack, _T_473) @[I2C.scala 381:17 437:26 448:23]
    node _T_485 = eq(UInt<3>("h4"), byteState) @[Conditional.scala 37:30]
    node _GEN_143 = mux(cmd_stop, UInt<3>("h5"), UInt<3>("h0")) @[I2C.scala 453:27 454:23 458:23]
    node _GEN_144 = mux(cmd_stop, UInt<2>("h2"), UInt<2>("h0")) @[I2C.scala 453:27 455:23 459:23]
    node _GEN_145 = mux(cmd_stop, UInt<1>("h0"), UInt<1>("h1")) @[I2C.scala 384:17 453:27 462:23]
    node _GEN_146 = mux(bitCmdAck, _GEN_143, byteState) @[I2C.scala 369:24 452:26]
    node _GEN_147 = mux(bitCmdAck, pad(_GEN_144, 4), bitCmd) @[I2C.scala 191:24 452:26]
    node _GEN_148 = and(bitCmdAck, _GEN_145) @[I2C.scala 384:17 452:26]
    node _GEN_149 = mux(bitCmdAck, receivedBit, receivedAck) @[I2C.scala 452:26 466:23 348:24]
    node _GEN_150 = or(bitCmdAck, cmd_ack) @[I2C.scala 452:26 468:23 471:23]
    node _T_488 = eq(UInt<3>("h5"), byteState) @[Conditional.scala 37:30]
    node _GEN_151 = mux(bitCmdAck, UInt<3>("h0"), byteState) @[I2C.scala 475:26 476:21 369:24]
    node _GEN_152 = mux(bitCmdAck, UInt<4>("h0"), bitCmd) @[I2C.scala 475:26 477:21 191:24]
    node _GEN_153 = mux(_T_488, _GEN_151, byteState) @[Conditional.scala 39:67 I2C.scala 369:24]
    node _GEN_154 = mux(_T_488, _GEN_152, bitCmd) @[Conditional.scala 39:67 I2C.scala 191:24]
    node _GEN_155 = and(_T_488, bitCmdAck) @[Conditional.scala 39:67 I2C.scala 384:17]
    node _GEN_156 = mux(_T_485, _GEN_146, _GEN_153) @[Conditional.scala 39:67]
    node _GEN_157 = mux(_T_485, _GEN_147, _GEN_154) @[Conditional.scala 39:67]
    node _GEN_158 = mux(_T_485, _GEN_148, _GEN_155) @[Conditional.scala 39:67]
    node _GEN_159 = mux(_T_485, _GEN_149, receivedAck) @[Conditional.scala 39:67 I2C.scala 348:24]
    node _GEN_160 = mux(_T_485, _GEN_150, _T_473) @[Conditional.scala 39:67 I2C.scala 381:17]
    node _GEN_161 = mux(_T_483, _GEN_140, _GEN_156) @[Conditional.scala 39:67]
    node _GEN_162 = mux(_T_483, _GEN_141, _GEN_157) @[Conditional.scala 39:67]
    node _GEN_163 = and(_T_483, bitCmdAck) @[Conditional.scala 39:67 I2C.scala 382:17]
    node _GEN_164 = mux(_T_483, _GEN_142, _GEN_160) @[Conditional.scala 39:67]
    node _GEN_165 = mux(_T_483, UInt<1>("h0"), _GEN_158) @[Conditional.scala 39:67 I2C.scala 384:17]
    node _GEN_166 = mux(_T_483, receivedAck, _GEN_159) @[Conditional.scala 39:67 I2C.scala 348:24]
    node _GEN_167 = mux(_T_481, _GEN_135, _GEN_161) @[Conditional.scala 39:67]
    node _GEN_168 = mux(_T_481, _GEN_136, _GEN_162) @[Conditional.scala 39:67]
    node _GEN_169 = mux(_T_481, _GEN_137, _GEN_163) @[Conditional.scala 39:67]
    node _GEN_170 = mux(_T_481, _T_473, _GEN_164) @[Conditional.scala 39:67 I2C.scala 381:17]
    node _GEN_171 = mux(_T_481, UInt<1>("h0"), _GEN_165) @[Conditional.scala 39:67 I2C.scala 384:17]
    node _GEN_172 = mux(_T_481, receivedAck, _GEN_166) @[Conditional.scala 39:67 I2C.scala 348:24]
    node _GEN_173 = mux(_T_479, _GEN_129, _GEN_167) @[Conditional.scala 39:67]
    node _GEN_174 = mux(_T_479, _GEN_130, _GEN_168) @[Conditional.scala 39:67]
    node _GEN_175 = and(_T_479, bitCmdAck) @[Conditional.scala 39:67 I2C.scala 383:17]
    node _GEN_176 = mux(_T_479, UInt<1>("h0"), _GEN_169) @[Conditional.scala 39:67 I2C.scala 382:17]
    node _GEN_177 = mux(_T_479, _T_473, _GEN_170) @[Conditional.scala 39:67 I2C.scala 381:17]
    node _GEN_178 = mux(_T_479, UInt<1>("h0"), _GEN_171) @[Conditional.scala 39:67 I2C.scala 384:17]
    node _GEN_179 = mux(_T_479, receivedAck, _GEN_172) @[Conditional.scala 39:67 I2C.scala 348:24]
    node _GEN_180 = mux(_T_477, _GEN_124, _GEN_173) @[Conditional.scala 40:58]
    node _GEN_181 = mux(_T_477, _GEN_125, _GEN_174) @[Conditional.scala 40:58]
    node _GEN_182 = mux(_T_477, go, _GEN_175) @[Conditional.scala 40:58]
    node _GEN_183 = mux(_T_477, UInt<1>("h0"), _GEN_176) @[Conditional.scala 40:58 I2C.scala 382:17]
    node _GEN_184 = mux(_T_477, _T_473, _GEN_177) @[Conditional.scala 40:58 I2C.scala 381:17]
    node _GEN_185 = mux(_T_477, UInt<1>("h0"), _GEN_178) @[Conditional.scala 40:58 I2C.scala 384:17]
    node _GEN_186 = mux(_T_477, receivedAck, _GEN_179) @[Conditional.scala 40:58 I2C.scala 348:24]
    node _GEN_187 = mux(arbLost, UInt<4>("h0"), _GEN_181) @[I2C.scala 371:18 372:17]
    node _GEN_188 = mux(arbLost, UInt<1>("h0"), _GEN_184) @[I2C.scala 371:18 373:17]
    node _GEN_189 = mux(arbLost, UInt<1>("h0"), _GEN_183) @[I2C.scala 371:18 374:17]
    node _GEN_190 = mux(arbLost, UInt<1>("h0"), _GEN_182) @[I2C.scala 371:18 375:17]
    node _GEN_191 = mux(arbLost, UInt<1>("h0"), _GEN_185) @[I2C.scala 371:18 376:17]
    node _GEN_192 = mux(arbLost, UInt<3>("h0"), _GEN_180) @[I2C.scala 371:18 377:17]
    node _GEN_193 = mux(arbLost, UInt<1>("h0"), _GEN_186) @[I2C.scala 371:18 378:17]
    node _T_541 = eq(auto_in_a_bits_opcode, UInt<3>("h4")) @[RegisterRouter.scala 55:36]
    node _T_542 = shr(auto_in_a_bits_address, 2) @[Edges.scala 183:34]
    node _T_537_bits_index = bits(_T_542, 9, 0) @[RegisterRouter.scala 54:18 56:19]
    node _T_1042 = bits(_T_537_bits_index, 2, 2) @[RegisterRouter.scala 62:24]
    node _T_1041 = bits(_T_537_bits_index, 1, 1) @[RegisterRouter.scala 62:24]
    node _T_1050 = cat(_T_1042, _T_1041) @[Cat.scala 30:58]
    node _T_1040 = bits(_T_537_bits_index, 0, 0) @[RegisterRouter.scala 62:24]
    node _T_1051 = cat(_T_1050, _T_1040) @[Cat.scala 30:58]
    node _T_613 = xor(_T_537_bits_index, UInt<10>("h4")) @[RegisterRouter.scala 62:24]
    node _T_614 = and(_T_613, UInt<10>("h3f8")) @[RegisterRouter.scala 62:24]
    node _T_616 = eq(_T_614, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_1124 = not(_T_616) @[RegisterRouter.scala 62:24]
    node _T_604 = xor(_T_537_bits_index, UInt<10>("h3")) @[RegisterRouter.scala 62:24]
    node _T_605 = and(_T_604, UInt<10>("h3f8")) @[RegisterRouter.scala 62:24]
    node _T_607 = eq(_T_605, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_595 = xor(_T_537_bits_index, UInt<10>("h2")) @[RegisterRouter.scala 62:24]
    node _T_596 = and(_T_595, UInt<10>("h3f8")) @[RegisterRouter.scala 62:24]
    node _T_598 = eq(_T_596, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_586 = xor(_T_537_bits_index, UInt<10>("h1")) @[RegisterRouter.scala 62:24]
    node _T_587 = and(_T_586, UInt<10>("h3f8")) @[RegisterRouter.scala 62:24]
    node _T_589 = eq(_T_587, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_578 = and(_T_537_bits_index, UInt<10>("h3f8")) @[RegisterRouter.scala 62:24]
    node _T_580 = eq(_T_578, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_1323 = and(auto_in_a_valid, auto_in_d_ready) @[RegisterRouter.scala 62:24]
    node _T_1325 = not(_T_541) @[RegisterRouter.scala 62:24]
    node _T_1326 = and(_T_1323, _T_1325) @[RegisterRouter.scala 62:24]
    node _T_1075 = dshl(UInt<1>("h1"), _T_1051) @[OneHot.scala 45:35]
    node _T_1080 = bits(_T_1075, 4, 4) @[RegisterRouter.scala 62:24]
    node _T_1361 = and(_T_1326, _T_1080) @[RegisterRouter.scala 62:24]
    node _T_1362 = and(_T_1361, _T_616) @[RegisterRouter.scala 62:24]
    node _T_707 = bits(auto_in_a_bits_mask, 3, 3) @[Bitwise.scala 27:51]
    node _T_723 = mux(_T_707, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12]
    node _T_706 = bits(auto_in_a_bits_mask, 2, 2) @[Bitwise.scala 27:51]
    node _T_719 = mux(_T_706, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12]
    node _T_725 = cat(_T_723, _T_719) @[Cat.scala 30:58]
    node _T_705 = bits(auto_in_a_bits_mask, 1, 1) @[Bitwise.scala 27:51]
    node _T_715 = mux(_T_705, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12]
    node _T_704 = bits(auto_in_a_bits_mask, 0, 0) @[Bitwise.scala 27:51]
    node _T_711 = mux(_T_704, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12]
    node _T_724 = cat(_T_715, _T_711) @[Cat.scala 30:58]
    node _T_726 = cat(_T_725, _T_724) @[Cat.scala 30:58]
    node _T_1001 = bits(_T_726, 7, 0) @[RegisterRouter.scala 62:24]
    node _T_1002 = not(_T_1001) @[RegisterRouter.scala 62:24]
    node _T_1004 = eq(_T_1002, UInt<8>("h0")) @[RegisterRouter.scala 62:24]
    node _T_1008 = and(_T_1362, _T_1004) @[RegisterRouter.scala 62:24]
    node _T_1015 = bits(auto_in_a_bits_data, 7, 0) @[RegisterRouter.scala 62:24]
    node _T_506 = cat(cmd_start, cmd_stop) @[I2C.scala 492:18]
    node _T_505 = cat(cmd_read, cmd_write) @[I2C.scala 492:18]
    node _T_507 = cat(_T_506, _T_505) @[I2C.scala 492:18]
    node _T_503 = cat(cmd_ack, UInt<2>("h0")) @[I2C.scala 492:18]
    node _T_504 = cat(_T_503, cmd_irqAck) @[I2C.scala 492:18]
    node _T_508 = cat(_T_507, _T_504) @[I2C.scala 492:18]
    node _T_510 = and(_T_508, UInt<8>("hfe")) @[I2C.scala 492:25]
    node nextCmd = mux(_T_1008, _T_1015, _T_510) @[I2C.scala 492:11 538:77 540:74]
    node _T_496 = bits(nextCmd, 0, 0) @[I2C.scala 491:38]
    node _T_498 = bits(nextCmd, 3, 3) @[I2C.scala 491:38]
    node _T_499 = bits(nextCmd, 4, 4) @[I2C.scala 491:38]
    node _T_500 = bits(nextCmd, 5, 5) @[I2C.scala 491:38]
    node _T_501 = bits(nextCmd, 6, 6) @[I2C.scala 491:38]
    node _T_502 = bits(nextCmd, 7, 7) @[I2C.scala 491:38]
    node _T_511 = or(cmdAck, arbLost) @[I2C.scala 495:16]
    node _GEN_194 = mux(_T_511, UInt<1>("h0"), _T_502) @[I2C.scala 495:28 496:15 491:7]
    node _GEN_195 = mux(_T_511, UInt<1>("h0"), _T_501) @[I2C.scala 495:28 497:15 491:7]
    node _GEN_196 = mux(_T_511, UInt<1>("h0"), _T_500) @[I2C.scala 495:28 498:15 491:7]
    node _GEN_197 = mux(_T_511, UInt<1>("h0"), _T_499) @[I2C.scala 495:28 499:15 491:7]
    node _GEN_198 = or(startCond, status_busy) @[I2C.scala 114:25 506:25 507:29]
    node _GEN_199 = mux(stopCond, UInt<1>("h0"), _GEN_198) @[I2C.scala 503:19 504:29]
    node _GEN_200 = mux(cmd_start, UInt<1>("h0"), status_arbLost) @[I2C.scala 114:25 513:25 514:29]
    node _GEN_201 = or(arbLost, _GEN_200) @[I2C.scala 510:18 511:29]
    node _T_522 = or(_T_511, status_irqFlag) @[I2C.scala 517:51]
    node _T_524 = not(cmd_irqAck) @[I2C.scala 517:73]
    node _T_525 = and(_T_522, _T_524) @[I2C.scala 517:70]
    reg statusReadReady : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), statusReadReady) @[I2C.scala 520:28]
    node _T_531 = not(statusReadReady) @[I2C.scala 524:14]
    node _GEN_202 = or(_T_531, statusReadReady) @[I2C.scala 524:32 525:21 520:28]
    node _GEN_203 = mux(_T_511, UInt<1>("h0"), _GEN_202) @[I2C.scala 521:28 522:21]
    node _T_543 = cat(auto_in_a_bits_source, auto_in_a_bits_size) @[Cat.scala 30:58]
    node _T_729 = neq(_T_1001, UInt<8>("h0")) @[RegisterRouter.scala 62:24]
    node _T_1030 = not(_T_729) @[RegisterRouter.scala 62:24]
    node _T_1031 = or(statusReadReady, _T_1030) @[RegisterRouter.scala 62:24]
    node _T_1285 = or(_T_1031, _T_1124) @[RegisterRouter.scala 62:24]
    node _GEN_232 = mux(eq(UInt<3>("h4"), _T_1051), _T_1285, UInt<1>("h1")) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_260 = eq(UInt<3>("h5"), _T_1051) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_233 = or(_GEN_260, _GEN_232) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_261 = eq(UInt<3>("h6"), _T_1051) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_234 = or(_GEN_261, _GEN_233) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_262 = eq(UInt<3>("h7"), _T_1051) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_235 = or(_GEN_262, _GEN_234) @[RegisterRouter.scala 62:{24,24}]
    node _T_1409 = mux(_T_541, _GEN_235, UInt<1>("h1")) @[RegisterRouter.scala 62:24]
    node _T_1066 = bits(_T_1075, 0, 0) @[RegisterRouter.scala 62:24]
    node _T_1329 = and(_T_1326, _T_1066) @[RegisterRouter.scala 62:24]
    node _T_1330 = and(_T_1329, _T_580) @[RegisterRouter.scala 62:24]
    node _T_744 = and(_T_1330, _T_1004) @[RegisterRouter.scala 62:24]
    node _GEN_204 = mux(_T_744, _T_1015, prescaler_lo) @[I2C.scala 109:25 RegField.scala 135:{88,92}]
    node _T_1067 = bits(_T_1075, 1, 1) @[RegisterRouter.scala 62:24]
    node _T_1337 = and(_T_1326, _T_1067) @[RegisterRouter.scala 62:24]
    node _T_1338 = and(_T_1337, _T_589) @[RegisterRouter.scala 62:24]
    node _T_788 = and(_T_1338, _T_1004) @[RegisterRouter.scala 62:24]
    node _GEN_205 = mux(_T_788, _T_1015, prescaler_hi) @[I2C.scala 109:25 RegField.scala 135:{88,92}]
    node _T_1068 = bits(_T_1075, 2, 2) @[RegisterRouter.scala 62:24]
    node _T_1345 = and(_T_1326, _T_1068) @[RegisterRouter.scala 62:24]
    node _T_1346 = and(_T_1345, _T_598) @[RegisterRouter.scala 62:24]
    node _T_859 = bits(_T_726, 6, 6) @[RegisterRouter.scala 62:24]
    node _T_863 = not(_T_859) @[RegisterRouter.scala 62:24]
    node _T_865 = not(_T_863) @[RegisterRouter.scala 62:24]
    node _T_876 = and(_T_1346, _T_865) @[RegisterRouter.scala 62:24]
    node _T_879 = bits(auto_in_a_bits_data, 6, 6) @[RegisterRouter.scala 62:24]
    node _GEN_207 = mux(_T_876, _T_879, control_intEn) @[I2C.scala 110:25 RegField.scala 135:{88,92}]
    node _T_898 = shl(control_intEn, 6) @[RegisterRouter.scala 62:24]
    node _T_903 = bits(_T_726, 7, 7) @[RegisterRouter.scala 62:24]
    node _T_907 = not(_T_903) @[RegisterRouter.scala 62:24]
    node _T_909 = not(_T_907) @[RegisterRouter.scala 62:24]
    node _T_920 = and(_T_1346, _T_909) @[RegisterRouter.scala 62:24]
    node _T_923 = bits(auto_in_a_bits_data, 7, 7) @[RegisterRouter.scala 62:24]
    node _GEN_208 = mux(_T_920, _T_923, control_coreEn) @[I2C.scala 110:25 RegField.scala 135:{88,92}]
    node _T_942 = shl(control_coreEn, 7) @[RegisterRouter.scala 62:24]
    node _GEN_263 = pad(_T_898, 8) @[RegisterRouter.scala 62:24]
    node _T_946 = or(_GEN_263, _T_942) @[RegisterRouter.scala 62:24]
    node _T_1069 = bits(_T_1075, 3, 3) @[RegisterRouter.scala 62:24]
    node _T_1353 = and(_T_1326, _T_1069) @[RegisterRouter.scala 62:24]
    node _T_1354 = and(_T_1353, _T_607) @[RegisterRouter.scala 62:24]
    node _T_964 = and(_T_1354, _T_1004) @[RegisterRouter.scala 62:24]
    node _GEN_209 = mux(_T_964, _T_1015, transmitData) @[I2C.scala 111:25 RegField.scala 135:{88,92}]
    node _T_1009 = cat(UInt<3>("h0"), status_transferInProgress) @[I2C.scala 535:89]
    node _T_1010 = cat(_T_1009, status_irqFlag) @[I2C.scala 535:89]
    node _T_1011 = cat(status_receivedAck, status_busy) @[I2C.scala 535:89]
    node _T_1012 = cat(_T_1011, status_arbLost) @[I2C.scala 535:89]
    node _T_1013 = cat(_T_1012, _T_1010) @[I2C.scala 535:89]
    node _GEN_210 = mux(_T_1008, UInt<1>("h0"), _GEN_203) @[I2C.scala 538:77 539:82]
    node _GEN_245 = mux(eq(UInt<3>("h1"), _T_1051), _T_589, _T_580) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_246 = mux(eq(UInt<3>("h2"), _T_1051), _T_598, _GEN_245) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_247 = mux(eq(UInt<3>("h3"), _T_1051), _T_607, _GEN_246) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_248 = mux(eq(UInt<3>("h4"), _T_1051), _T_616, _GEN_247) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_249 = or(_GEN_260, _GEN_248) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_250 = or(_GEN_261, _GEN_249) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_251 = or(_GEN_262, _GEN_250) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_253 = mux(eq(UInt<3>("h1"), _T_1051), prescaler_hi, prescaler_lo) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_254 = mux(eq(UInt<3>("h2"), _T_1051), _T_946, _GEN_253) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_255 = mux(eq(UInt<3>("h3"), _T_1051), receivedData, _GEN_254) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_256 = mux(eq(UInt<3>("h4"), _T_1051), _T_1013, _GEN_255) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_257 = mux(eq(UInt<3>("h5"), _T_1051), UInt<8>("h0"), _GEN_256) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_258 = mux(eq(UInt<3>("h6"), _T_1051), UInt<8>("h0"), _GEN_257) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_259 = mux(eq(UInt<3>("h7"), _T_1051), UInt<8>("h0"), _GEN_258) @[RegisterRouter.scala 62:{24,24}]
    node _T_1443 = mux(_GEN_251, _GEN_259, UInt<8>("h0")) @[RegisterRouter.scala 62:24]
    node _GEN_267 = mux(reset, UInt<9>("h0"), _GEN_117) @[I2C.scala 112:{25,25}]
    node _GEN_268 = mux(reset, UInt<4>("h7"), _GEN_2) @[I2C.scala 132:{22,22}]
    node _GEN_269 = mux(reset, UInt<4>("h7"), _GEN_3) @[I2C.scala 133:{22,22}]
    auto_int_out_0 <= and(status_irqFlag, control_intEn) @[I2C.scala 552:35]
    auto_in_a_ready <= and(auto_in_d_ready, _T_1409) @[RegisterRouter.scala 62:24]
    auto_in_b_valid <= UInt<1>("h0") @[Nodes.scala 329:76 RegisterRouter.scala 80:22]
    auto_in_b_bits_opcode <= UInt<3>("h0") @[LazyModule.scala 171:31]
    auto_in_b_bits_param <= UInt<2>("h0") @[LazyModule.scala 171:31]
    auto_in_b_bits_size <= UInt<2>("h0") @[LazyModule.scala 171:31]
    auto_in_b_bits_source <= UInt<7>("h0") @[LazyModule.scala 171:31]
    auto_in_b_bits_address <= UInt<29>("h0") @[LazyModule.scala 171:31]
    auto_in_b_bits_mask <= UInt<4>("h0") @[LazyModule.scala 171:31]
    auto_in_b_bits_data <= UInt<32>("h0") @[LazyModule.scala 171:31]
    auto_in_c_ready <= UInt<1>("h1") @[Nodes.scala 329:76 RegisterRouter.scala 81:22]
    auto_in_d_valid <= and(auto_in_a_valid, _T_1409) @[RegisterRouter.scala 62:24]
    auto_in_d_bits_opcode <= pad(_T_541, 3) @[Nodes.scala 329:76 RegisterRouter.scala 77:19]
    auto_in_d_bits_param <= UInt<2>("h0") @[Edges.scala 646:17 648:15]
    auto_in_d_bits_size <= bits(_T_543, 1, 0) @[RegisterRouter.scala 73:35]
    auto_in_d_bits_source <= bits(_T_543, 8, 2) @[RegisterRouter.scala 72:35]
    auto_in_d_bits_sink <= UInt<1>("h0") @[Edges.scala 646:17 651:15]
    auto_in_d_bits_data <= pad(_T_1443, 32) @[RegisterRouter.scala 62:{24,24}]
    auto_in_d_bits_error <= UInt<1>("h0") @[Edges.scala 646:17 653:15]
    auto_in_e_ready <= UInt<1>("h1") @[Nodes.scala 329:76 RegisterRouter.scala 82:22]
    io_port_scl_out <= UInt<1>("h0") @[I2C.scala 119:19]
    io_port_scl_oe <= not(sclOen) @[I2C.scala 178:21]
    io_port_sda_out <= UInt<1>("h0") @[I2C.scala 120:19]
    io_port_sda_oe <= not(sdaOen) @[I2C.scala 181:21]
    TLMonitor_reset <= reset
    TLMonitor_io_in_a_ready <= and(auto_in_d_ready, _T_1409) @[RegisterRouter.scala 62:24]
    TLMonitor_io_in_a_valid <= auto_in_a_valid @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_opcode <= auto_in_a_bits_opcode @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_param <= auto_in_a_bits_param @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_size <= auto_in_a_bits_size @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_source <= auto_in_a_bits_source @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_address <= auto_in_a_bits_address @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_mask <= auto_in_a_bits_mask @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_c_valid <= auto_in_c_valid @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_d_ready <= auto_in_d_ready @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_d_valid <= and(auto_in_a_valid, _T_1409) @[RegisterRouter.scala 62:24]
    TLMonitor_io_in_d_bits_opcode <= pad(_T_541, 3) @[Nodes.scala 329:76 RegisterRouter.scala 77:19]
    TLMonitor_io_in_d_bits_size <= bits(_T_543, 1, 0) @[RegisterRouter.scala 73:35]
    TLMonitor_io_in_d_bits_source <= bits(_T_543, 8, 2) @[RegisterRouter.scala 72:35]
    TLMonitor_io_in_e_valid <= auto_in_e_valid @[LazyModule.scala 171:31 Nodes.scala 329:76]
    prescaler_hi <= mux(reset, UInt<8>("hff"), _GEN_205) @[I2C.scala 109:{25,25}]
    prescaler_lo <= mux(reset, UInt<8>("hff"), _GEN_204) @[I2C.scala 109:{25,25}]
    control_coreEn <= mux(reset, UInt<1>("h0"), _GEN_208) @[I2C.scala 110:{25,25}]
    control_intEn <= mux(reset, UInt<1>("h0"), _GEN_207) @[I2C.scala 110:{25,25}]
    transmitData <= mux(reset, UInt<8>("h0"), _GEN_209) @[I2C.scala 111:{25,25}]
    receivedData <= bits(_GEN_267, 7, 0) @[I2C.scala 112:{25,25}]
    cmd_start <= mux(reset, UInt<1>("h0"), _GEN_194) @[I2C.scala 113:{25,25}]
    cmd_stop <= mux(reset, UInt<1>("h0"), _GEN_195) @[I2C.scala 113:{25,25}]
    cmd_read <= mux(reset, UInt<1>("h0"), _GEN_196) @[I2C.scala 113:{25,25}]
    cmd_write <= mux(reset, UInt<1>("h0"), _GEN_197) @[I2C.scala 113:{25,25}]
    cmd_ack <= mux(reset, UInt<1>("h0"), _T_498) @[I2C.scala 113:{25,25} 491:7]
    cmd_irqAck <= mux(reset, UInt<1>("h0"), _T_496) @[I2C.scala 113:{25,25} 491:7]
    status_receivedAck <= mux(reset, UInt<1>("h0"), receivedAck) @[I2C.scala 114:{25,25} 502:22]
    status_busy <= mux(reset, UInt<1>("h0"), _GEN_199) @[I2C.scala 114:{25,25}]
    status_arbLost <= mux(reset, UInt<1>("h0"), _GEN_201) @[I2C.scala 114:{25,25}]
    status_transferInProgress <= mux(reset, UInt<1>("h0"), _T_451) @[I2C.scala 114:{25,25} 516:29]
    status_irqFlag <= mux(reset, UInt<1>("h0"), _T_525) @[I2C.scala 114:{25,25} 517:29]
    filterCnt <= mux(reset, UInt<14>("h0"), _GEN_1) @[I2C.scala 123:{22,22}]
    fSCL <= bits(_GEN_268, 2, 0) @[I2C.scala 132:{22,22}]
    fSDA <= bits(_GEN_269, 2, 0) @[I2C.scala 133:{22,22}]
    sSCL <= or(reset, _T_264) @[I2C.scala 139:{22,22,22}]
    sSDA <= or(reset, _T_274) @[I2C.scala 140:{22,22,22}]
    dSCL <= or(reset, sSCL) @[I2C.scala 142:{22,22,22}]
    dSDA <= or(reset, sSDA) @[I2C.scala 143:{22,22,22}]
    dSCLOen <= io_port_scl_oe @[I2C.scala 145:22]
    startCond <= mux(reset, UInt<1>("h0"), _T_285) @[I2C.scala 149:{22,22,22}]
    stopCond <= mux(reset, UInt<1>("h0"), _T_291) @[I2C.scala 150:{22,22,22}]
    slaveWait <= mux(reset, UInt<1>("h0"), _T_307) @[I2C.scala 158:{22,22} 159:13]
    clkEn <= or(reset, _T_319) @[I2C.scala 161:{22,22}]
    cnt <= mux(reset, UInt<16>("h0"), _GEN_6) @[I2C.scala 162:{22,22}]
    sclOen <= or(reset, _GEN_111) @[I2C.scala 177:{23,23}]
    sdaOen <= or(reset, _GEN_112) @[I2C.scala 180:{23,23}]
    sdaChk <= mux(reset, UInt<1>("h0"), _GEN_113) @[I2C.scala 183:{23,23}]
    transmitBit <= mux(reset, UInt<1>("h0"), _GEN_188) @[I2C.scala 185:{24,24}]
    receivedBit <= mux(_T_343, sSDA, receivedBit) @[I2C.scala 187:24 188:17 186:24]
    bitCmd <= mux(reset, UInt<4>("h0"), _GEN_187) @[I2C.scala 191:{24,24}]
    bitCmdStop <= mux(reset, UInt<1>("h0"), _GEN_9) @[I2C.scala 192:{24,24}]
    bitCmdAck <= mux(reset, UInt<1>("h0"), _GEN_110) @[I2C.scala 196:{24,24}]
    bitState <= mux(reset, UInt<5>("h0"), _GEN_109) @[I2C.scala 203:{24,24}]
    arbLost <= mux(reset, UInt<1>("h0"), _T_363) @[I2C.scala 205:{24,24,24}]
    load <= mux(reset, UInt<1>("h0"), _GEN_190) @[I2C.scala 345:{24,24}]
    shift <= mux(reset, UInt<1>("h0"), _GEN_189) @[I2C.scala 346:{24,24}]
    cmdAck <= mux(reset, UInt<1>("h0"), _GEN_191) @[I2C.scala 347:{24,24}]
    receivedAck <= mux(reset, UInt<1>("h0"), _GEN_193) @[I2C.scala 348:{24,24}]
    bitCnt <= mux(reset, UInt<3>("h0"), _GEN_115) @[I2C.scala 351:{24,24}]
    byteState <= mux(reset, UInt<3>("h0"), _GEN_192) @[I2C.scala 369:{24,24}]
    statusReadReady <= or(reset, _GEN_210) @[I2C.scala 520:{28,28}]
